The present invention concerns the fabrication of integrated circuits and pertains particularly to a reliable process for forming gates with different gate oxide thicknesses while avoiding polysilicon stringers.
For integrated circuits which utilize 3.3 volt technology, the nominal power supply is at 3.3 volts while the signals may switch between 3.3 volts and 0 volts. When constructing an integrated circuit which uses 3.3 volt technology, it is often desirable that some of the transistors on the integrated circuit be able to tolerate placement of 5 volt signals on the gate of the transistors used for input/output (I/O) cells of the integrated circuit. When the gate oxide thickness for the 3.3 volt technology cannot support 5 volt operation, a dual gate oxide process is used. That is, the thickness of the gate oxide for transistors in the core of the integrated circuit is thinner than the gate oxide for transistors in the I/O cells of the integrated circuit where the transistors are 5 volt tolerant.
Current dual gate oxide processes generally begin by growing a thick gate oxide which is optimized for transistors which are able to tolerate 5 volt signals. Within the I/O cells, gates for 5 volt tolerant transistors are defined. Polysilicon is deposited and then etched to form the gates for 5 volt tolerant transistors. In the core of the integrated circuit, the thick gate oxide which is suitable for transistors which are able to tolerate 5 volt signals is too thick for transistors which are controlled by 3.3 volt signals. Therefore, for transistor cells in the core of the integrated circuits, the thick gate oxide is stripped and a thinner gate oxide is grown which is suitable for transistors which are controlled by 3.3 volt signals.
When stripping the thick gate oxide for transistor cells in the core of the integrated circuit, the thick gate oxide within the I/O cells which is exposed will also be stripped, possibly resulting in undercutting the gate oxide under the polysilicon gates which have been formed for 5 volt tolerant transistors. This can be avoided by masking I/O cells with photo resist. However, when the photo resist is removed from the I/O cells, this can result in damage or contamination of the oxides, which can result in reduced product yield or reliability.
Once the thinner gate oxide which is suitable for transistors which are controlled by 3.3 volt signals is grown, gates are formed for transistors within the core of the integrated circuit. For example, for polycide gates, a polysilicon (poly2) layer, a metal layer (such as titanium-tungsten (TiW)) and a dielectric layer (such as TEOS oxide) are deposited and patterned (using an anisotropic etch) to define the gate regions. The process of forming the polycide gates in the core region of the integrated circuits often results in the formation of polysilicon (poly2) strings on the sidewalls of the gates for transistors within the I/O cells. The poly2 stringers can cause shorting between transistors within the I/O cells. In addition, the poly2 stringers can also prevent proper alignment of subsequent lightly doped drain (Ldd) implants.
Because of the drawbacks of present processes, it is desirable to come up with a dual gate oxide process which will strengthen electrostatic discharge (ESD) tolerance, integrity of the gate oxide and increase hot carrier reliability in 5 volt tolerant I/O cells developed for a 3.3 volt technology. In doing this, it is also desirable to eliminate the flaws inherent in current processes, such as gate oxide damage or contamination, Ldd implant misplacement, sidewall string susceptibility, and poor critical dimension (CD) control.